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MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
DESCRIPTION
The M64893 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using Bip process. It contains the prescaler with operating up to 1.3GHz, 4 band drivers and Op. Amp for direct tuning.
PIN CONFIGURATION (TOP VIEW)
PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2
fin GND VCC1 VCC2 BS4
1 2
16 Xin 15 ENA
FEATURES
3 4 5 6 7 8
14 DATA 13 CLK
CRYSTAL OSCILLATOR ENABLE INPUT DATA INPUT CLOCK INPUT
M64893FP/GP
* * * * * * * * *
4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V) Built-in Op. Amp for direct tuning voltage output (33V) Low power dissipation (Icc=20mA, Vcc1=5V) Built-in prescaler with input amplifier (Fmax=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor ) X'tal 4MHz is used to realize 1 type of tuning steps (Division ratio 1/640) Serial data input. (3 wire bus ) Built-in Power on reset system Small package (SOP/SSOP)
BAND SWITCHING OUTPUTS
BS3 BS2 BS1
12 LD/ftest LD/ftest OUTPUT SUPPLY 11 VCC3 VOLTAGE 3 TUNING 10 Vtu OUTPUT 9 Vin FILTER INPUT
Outline 16P2S-A (FP) 16P2Z-A (GP)
APPLICATION
TV, VCR tuners
FUNCTION
RECOMMENDED OPERATING CONDITION
Supply voltage range..............................................V CC1=4.5 to 5.5V VCC2=VCC1 to 13.2V VCC3=28 to 35V Rated supply voltage...........................................................V CC1=5V VCC2=12V VCC3=33V
* * * * * * *
2-modulus prescaler (1/32 and 1/33) Built-in 4MHz crystal oscillator and reference divider Programmable divider (10-bit M counter, 5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op. Amp for direct tuning
1
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
BLOCK DIAGRAM
CRYSTAL OSCILLATOR X in 16 ENABLE INPUT ENA 15 DATA INPUT DATA 14 CLOCK INPUT CLK 13 LD/ftest OUTPUT LD/ftest 12 SUPPLY VOLTAGE 3 VCC3 11 TUNING OUTPUT Vtu 10 FILTER INPUT Vin 9
OSC
19-BIT SHIFT REGISTER LATCH
VCC1
DIVIDER 10 10-BIT M COUNTER 1/32,1/33 5 5-BIT S COUNTER 4 1/8 P.O RESET BIAS BAND DRIVER PHASE DETECTOR CHARGE PUMP LOCK DETECTOR AMP
AMP
1 f in PRESCALER INPUT
2 GND
3 VCC1 SUPPLY VOLTAGE 1
4 VCC2 SUPPLY VOLTAGE 2
5 BS4
6 BS3
7 BS2
8 BS1
BAND SWITCHING OUTPUTS
2
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
DESCRIPTION OF PIN
Pin No. 1 2 3 4 5 6 7 8 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0V. Power supply voltage terminal. 5.0V 0.5V Power supply for band switching, Vcc 1 to 13.2V PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fref), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35V When 19 bit data is input,lock detector is output. When 27 bit data is input, lock detector is output, the programmable freq. Divider output and reference freq. Output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the 19th pulse of the clock signal falls. 4.0MHz crystal oscillator is connected.
9
Vin
Filter input (Charge pump output) Tuning output Power supply voltage 3 Lock detect/Test port Clock input Data input Enable input This is connected to the crystal oscillator
10 11 12 13 14 15 16
Vtu VCC3 LD/ftest CLK DATA ENA Xin
ABSOLUTE MAXIMUM RATINGS (Ta=-20C to +75C, unless otherwise noted)
Symbol VCC1 VCC2 VCC3 VI VO VBSOFF IBSON tBSON Pd Topr Tstg Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Conditions Pin3 Pin4 Pin11 Not to exceed VCC1 LD output Ratings 6.0 14.4 36.0 6.0 6.0 14.4 Per 1 band output circuit 50mA per 1 band output circuit 3circuit are pn at same time Ta=+75C 50.0 10 470 -20 to +75 -40 to +125 Unit V V V V V V mA sec mW C C
RECOMMENDED OPERATING CONDITIONS (Ta=-20C to +75C, unless otherwise noted)
Symbol VCC1 VCC2 VCC3 fopr1 fopr2 IBDL Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Conditions Pin3 Pin4 Pin11 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. Ratings 4.5 to 5.5 VCC1 to 13.2 28 to 35 4.0 80 to 1,300 0 to 40 Unit V V V MHz MHz mA
3
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR ELECTRICAL CHARACTERISTICS (Ta=-20C to +75C, Vcc1=5.0V, Vcc2=12V, Vcc3=33V, unless otherwise noted)
Symbol VIH VIL IIH IIL IIL VOH VOL VBS IOLK2 VTOH VTOL ICPH ICPL ICPLK ICC1 ICC2A ICC2B ICC2C ICC3 Input pin Parameter "H" input voltage "L" input voltage "H" input current "L" input current "L" input current "H" output voltage "L" output voltage Output voltage Leak current Output voltage "H" Output voltage "L" "H" output current "L" output current Leak current Test pin 13 to 15 13 to 15 13 to 15 13, 15 14 12 12 5 to 8 5 to 8 10 10 9 9 9 3 4 4 4 11 Test conditions Min. 3.0 - - - - 5.0 - 11.6 - 32.5 - - - - - - - - - Limits Typ. Max. Unit V V A A A V V V A V V A A nA mA mA mA mA mA
Lock output Band SW Tuning output Charge pump
VCC1=5.5V, Vi=4.0V VCC1=5.5V, Vi=0.4V VCC1=5.5V, Vi=0.4V VCC1=5.5V VCC1=5.5V VCC2=12V, Io=-40mA VCC2=12V band SW is OFF VCC3=33V VCC3=33V VCC1=5.0V, Vo=1V VCC1=5.0V, Vo=1V VCC1=5.0V, Vo=2.5V VCC1=5.5V VCC2=12V VCC2=12V VCC2=12V Io=-40mA VCC3=33V Output ON
VCC1+0.3 - - 1.5 - 10 -6 -10 -18 -30 - - 0.3 0.5 11.8 - - -10 - - 0.2 0.4 270 370 70 110 - 50
Supply current 1 4 circuits: OFF Supply 1 circuits: ON, current 2 Output: OPEN Output current 40mA Supply current 3
20 - 6.0 46.0 3.0
30 0.3 8.0 48.0 4.0
Note. Typical values are measured at VCC1=5.0V, VCC2=12V, VCC3=33V, Ta=+25C.
SWITCHING CHARACTERISTICS (Ta=-20C to +75C, VCC1=5.0V, VCC2=12V, VCC3=33V, unless otherwise noted)
Symbol fopr2 Parameter Prescaler operating frequency Test pin 1 Test conditions VCC1=4.5 to 5.5V Vin=Vinmin to Vinmax 80 to 100MHz 100 to 200MHz VCC1=4.5 200 to 800MHz to 5.5V 800 to 1000MHz 1000 to 1300MHz Min. 80 -24 -27 -30 -27 -18 1 2 1 3 3 1 - - 5 5 Limits Typ. - - - - - - - - - - - - - - - - - - - - - 1 1 - - Max. 1300 4 4 4 4 4 Unit MHz
Vin
Operating input voltage
1
dBm
tPWC tSU (D) tH (D) tSU (E) tH (E) tINT tr tf tbt tbcl
Clock pulse width Data setup time Data hold time Enable setup time Enable hold time Enable data interval time Rise time Fall time Next enable prohibit time Next clock prohibit time
VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V 13, 14, 15 VCC1=4.5 to 5.5V 13, 14, 15 VCC1=4.5 to 5.5V 15 VCC1=4.5 to 5.5V 13, 15 VCC1=4.5 to 5.5V
13 14 14 15 15 15, 14
s s s s s s s s s s
4
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
METHOD OF SETTING DATA
The frequency demultiplying ratio uses 15bits. Setting up the band switching output uses 4bits. The test mode data uses 8bits. The total bits used is 27bits. Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal. The program counter data is read into the latch by the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 19th pulse of the enable signal, only the band SW data is updated and other data is ignored. The data is latched at the 19th pulse of the clock signal. At this time, 1/640 frequency division ratio is used. Clock signals after the above are invalid.
ENA BS4 DATA BS3 BS2 BS1 29 M9 28 M8 27 M7 26 M6 25 M5 24 M4 23 M3 22 M2 21 M1 20 M0 24 S4 23 S3 22 S2 21 S1 20 S0
CLK BAND SW DATA M COUNTER DIVISION RATIO SETTING READ INTO LATCH S COUNTER DIVISION RATIO SETTING READ INTO LATCH
HOW TO SET THE DIVIDING RATIO OF THE PROGRAMMABLE DIVIDER
Total division N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 (32M+S) M: 10 bit main counter division S: 5 bit swallow counter division The M and S counters are binary the possible ranges of division are as follows. 32M1023 0S31 Therefore, the range of division N is 8,192 to 262,136. The tuning frequency fVCO is given in the following equations. fVCO =fREFxN =6.25x8x(32M+S) =50.0x(32M+S) [kHz] But, the tuning frequency range is 51.2MHz to 1300MHz from the maximum prescaler operating frequency.
TEST MODE DATA SET UP METHOD
The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls. (1) When transferring 3-wire 27 bit data
ENA 1 CLK BAND SW DATA M COUNTER DIVISION RATIO SETTING S COUNTER DIVISION RATIO SETTING SI CP T2 T1 T0 RSa RSb OS TEST DATA SETTING READ INTO LATCH 19 20 27
5
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
(2) Test-mode bit setting X CP RSa, RSb OS SI :Random, 0 or 1.normal "0" :Set up the charge pump current value :Set the frequency division of the standard frequency :Set up the tuning amplifier :1 Only (It is prohibit to "0 ")
Set up for the reference frequency division ratio RSa 1 0 X RSb 1 1 0 Division ratio 1/512 1/1024 1/640
T0, T1, and T2 :Set up test modes
Set up the tuning amplifier OS 0 1 Tuning voltage output ON OFF Mode Normal Test
Setting up the charge pump current of the phase comparator CP 0 1 Charge pump current 70A 270A Mode Test Normal
POWER ON RESET OPERATION
(Initial state the power is turned ON) BS4 to BS1 : OFF : High impedance : OFF : 270A : 1/640 : "H"
Setting up for the test mode T2 T1 T0 Charge pump 0 0 X Normal operation 0 1 1 1 1 1 X High impedance 1 0 Sink 1 1 Source 0 0 High impedance 0 1 High impedance 12 pin output LD LD LD LD fREF f1/N Mode
Normal operation
Charge pump Tuning amplifier Charge pump current Frequency divider ratio Lock detect
Test mode Test mode Test mode Test mode Test mode
TIMING DIAGRAM
tr tf VIH 10% tINT tINT tBT VIH 90% 10% VIL tr 90% 10% VIL tPWC tSU(D) tSU(E) tH(D) tr tf tH(E) tBCL tf VIH
ENABLE 10%
90% 1.5V
90%
VIL
90% DATA 1.5V 10%
CLOCK
90% 1.5V 10%
CRYSTAL OSCILLATOR CONNECTION DIAGRAM 16
18pF Crystal oscillator characteristics Actual resistance: less than 300 Load capacitance : 20pF
4MHz
6
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
APPLICATION EXAMPLE
BUILT-IN PLL TUNER +5V Vcc1 to 12V UHF VHF
1000p
-
10
3
M64893FP/GP
-
5
SW
18 Vcc2 47k BS4 11
BS4 +B
4
5 47k BS3 12
BS3 IF
IF
1 TEST 47k BS2 13 M5493X series 3 DATA 14 BS1 14
6 4-BAND TUNER
BS2
7 47k
BS1
8 fIN 17 MCU 4 CLK 13 GND 16 15 2 EN 15 PD 20 LD/f1/N 12 XIN +5V 16 6 XOUT 7 GND 8 9 10 10 9 1000pF 0.1
1000p
Lo AGC
AGC
1.5n
VT
56k
56k
AFT
2.2n 100p
18p 4MHz -
11 +33V BT
Note) Filter constant is for reference. Add a capacitor to stabilize the circuit.
Units Resistance : Capacitance : F
7

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